Serial Port Controller of the PS/2 systems. The serial port is controlled by a NS16550 serial communications controller. It is programmable and supports asynchronous communications. The controller automatically adds and removes start, stop, and parity bits. A programmable baud rate generator allows operation from 50 baud to 19,200 baud [1]. The port supports 5-,6-,7-, and 8-bit characters with 1, 1.5, or 2 stop bits. A prioritized interrupt system controls transmit, receive, error, and line status as well as data-set interrupts. The NS16550 controller is functionally compatible to the NS16450 controller. To programs, the NS16550 appears to be identical to the serial portion of the IBM Personal Computer AT Serial/Parallel adapter. Support for the controller is restricted to the functions which are identical to the NS16450 [2]. Using the controller in the FIFO mode may result in non-detectable data errors [3]. The serial controller provides the following functions: o Full double buffering in the character mode, eliminating the need for precise synchronization o False-start bit detection o Line-break detection and generation o Modem control functions Clear to send (CTS) Request to send (RTS) Data set ready (DSR) Data terminal ready (DTR) Ring indicator (RI) Data carrier detect (DCD) --- 1) 19,200 limit is pure crap. The port itself can handle 115,200 baud operation OK, but the interrupt latency sets the practical limit to interrupt handled I/O at 34,800 baud. 19,200 baud is upper limit specified in RS-232C standard description, however, wicked design of the PS/2 Model 80 (and possibly others) do not allow using 115,200 baud speed even in polled mode. 2) Don't believe it. The support allows you only to do polled I/O and we all know what it means. 3) This is kind a misleading. What the IBM engineers really mean with this is that _they_ cannot handle NS16550 in FIFOed mode. Several communication libraries and FOSSIL drivers prove, that all it requires is a little higher IQ. Communications Application The serial output port can be addressed as either serial output port 1 or serial output port 2. In this section port addressed contain and n. The n can be either 3 for Serial 1 or 2 for Serial 2. Two interrupt lines are provided to the system. Interrupt level 4 (IRQ) is for Serial 1 and interrupt level 3 (IRQ3) is for Serial 2. To allow the controller to send interrupts to the interrupt controller, bit 3 of the modem control register must be set to 1 [1]. At this point, any interrupts allowed by the interrupt enable register will cause an interrupt. The data format is as follows: ÚÄÄÄÄÄ¿ ÚÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄ mark ³start³ D0 ³ D1 ³ D2 ³ D3 ³ D4 ³ D5 ³ D6 ³ D7 ³Parit³ Stop ÀÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÙ Data bit 0 is the first bit to be sent or received. The controller automatically inserts the start bit, the correct parity bit (if programmed to do so), and the stop bits. --- 1) This is only serial controller side of the story, of course. You have to enable the interrupt channel on interrupt controller also, before any interrupts can occur. This additional bit hardwired on serial interface allows you to temporarily disable interrupts without releasing interrupt channel, which may be useful from time to time. Programmable Baud-Rate Generator The controller has a programmable baud-rate generator that can divide the clock input (1.8432 MHz) by any divisor from 1 to 65535. The output frequency of the baud-rate generator is the baud rate multiplied by 16. Two 8-bit latches store the divisor in a 16-bit binary format. These divisor latches must be loaded during setup to ensure desired operation of the generator. When either of the divisor latches is loaded, a 16-bit baud counter is immediately loaded. This prevents long counts on the first load. Registers The controller has a number of accessible registers. The system programmer may gain access to or control any of the controller registers through the system microprocessor. These registers are used to control the controller operations and to transmit and receive data. Specific registers are selected according to the following figure: DLAB* Port R/W Register State address 0 nF8 W Transmitter holding register 0 nF8 R Receiver buffer register 1 nF8 R/W Divisor Latch, low byte 1 nF9 R/W Divisor Latch, high byte 0 nF9 R/W Interrupt enable register X nFA R Interrupt identification register X nFA W FIFO control register [1] X nFB R/W Line control register X nFC R/W Modem control register X nFD R Line status register X nFE R Modem status register X nFF R/W Scratch register * DLAB state is controlled by bit 7 of the line control register. --- 1) As IBM engineers cannot handle FIFOes, this is all information they will provide to the other people about this topic. Transmitter Holding Register (hex nF8) The transmitter holding register (THR) contains the character to be sent. Bit 0 is the least significant bit and the first bit serially sent. Receiver buffer register (hex nF8) The receiver buffer register (RBR) contains the received character. Bit 0 is the least significant bit and the first bit received serially. Divisor Latch Register LSB (hex nF8) Divisor Latch Register MSB (hex nF9) The divisor latch registers are used to program the baud rate generator. The values in these two registers form the divisor of the clock input (1.8432 MHz), which establishes the desired baud rate. The divisor can be calculated by following formula: divisor=115200/baud where baud is the baud rate desired. Interrupt Enable Register (hex nF9) This 8-bit register allows the four types of controller interrupts to separately activate the chip-interrupt output signal. The interrupt system can be totally disabled by clearing bits 0 through 3 of the interrupt enable register. Similarly, by setting appropriate bits of this register to 1, selected interrupts can be enabled. Disabling the interrupts inhibits the chip-interrupts output signal from the controller. All other system functions operate normally, including the setting of the line status and modem status registers. Bit Function 7-4 Reserved, always cleared to 0 3 Modem status interrupt enable 2 Line status interrupt enable 1 Transmitter holding register empty interrupt enable 0 Received data available interrupt enable Interrupt Identification Register (hex nFA) In order to minimize programming overhead during data character transfers, the controller prioritizes interrupts into four levels (high to low order): Line status changed Received data available Transmitter holding register empty Modem status changed Information about pending interrupt is stored in the interrupt identification register. When the interrupt identification register is addressed, the pending interrupt with the highest priority is held and no other interrupts are acknowledged until the system microprocessor services the interrupt. Bit Functions 7-3 Reserved, always set to 0. 2 Interrupt ID bit 1 1 Interrupt ID bit 0 0 No interrupt pending. If this bit is set to 1, no interrupt is pending and polling (if used) continues. When this bit is cleared to 0, an interrupt is pending and the contents of this register can be used as a pointer to the appropriate interrupt service routine. Interrupt ID bits select service functions as follows Bits Priority Type Cause Interrupt reset control 2 1 1 1 Highest Receiver Overrun, parity or Read the line status register line framing error or status break interrupt. 1 0 Second Received Data in receiver Read the receiver buffer data buffer register available 0 1 Third Transmit Ready to send next Read interrupt ID register holding byte or write to transmitter register holding register empty 0 0 Fourth Modem Change in signal Read the modem status register status status from modem Line Control Register (hex nFB) The format of asynchronous communications is programmed through the line control register. Bit Function 7 Divisor Latch Access bit. This bit must be set to 1 during a read or write operation to gain access to divisor latches of the baud-rate generator. It must be cleared to 0 to gain access to the receiver buffer, transmitter holding, or interrupt enable registers. 6 Set break. When this bit is set to 1, serial output is forced to spacing state and remains there regardless of other transmitter activity. 5 Stick parity. When bits 5,4, and 3 are set to 1, the parity bit is sent and checked as a logical 0. When bits 5 and 3 are set to 1, and bit 4 is cleared to 0, parity bit is sent and checked as a logical 1. 4 Even parity select. When this bit and bit 3 are set to 1, an even number of logical ones are transmitted and checked in the data word bits and parity bit. When this bit is cleared to 0 and bit 3 is set to 1, an odd number of logical ones are transmitted and checked in the data word bits and parity bit. 3 Parity enable. When set to 1, a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and stop bit. The parity bit is used to produce an even or odd number of ones when the data-word bits and the parity bit are summed. 2 Number of stop bits. When this bit is cleared to 0, one stop bit will be sent. When this bit is set to 1, two stop bits will be sent, except when the word length is 5 bits, in which case 1-1/2 stop bits will be sent. 1-0 Word length. These two bits specify the number of bits in each serial character that is sent or received. Word length is selected as shown in the following figure. Bit 1 0 Word length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits Modem Control Register (hex nFC) This 8-bit register controls the data exchange with the modem, data set, or peripherial device emulating a modem. Bit Function 7-5 Reserved, set to 0 4 Loop. This bit provides a loopback feature for diagnostic testing of the serial port. When this bit is set to 1: o Transmitter serial output is set to a marking state. o Receiver serial input is disconnected. o Output of the transmitter shift register is "looped back" to the receiver shift register input. (shift register are not accessible NS16550 registers) o The modem control inputs (CTS, DSR, DCD, and RI) are dis- connected. o The modem control outputs (DTR, RTS, OUT1, and OUT2) are internally connected to the four modem control inputs. o The modem control output pins are forced inactive. When the serial port is in the diagnostics mode, transmitted data is immediately received. This feature allows the system microprocessor to verify the transmit and receive data paths of the serial port. The interrupt system is fully operational in the diagnostics mode, but modem status sources are lower four bits of the modem control register, of course. 3 Out 2. This bit controls the auxiliary user-designated interrupt enable signal. Setting this bit to 1 allows interrupts to enter the computer bus. 2 Out 1. This bit functions like Out 2, but is left unused in IBM design. This is normally set inactive. 1 Request to send. 1 forces RTS signal active. 0 Data terminal ready. 1 forces DTR signal active. Line status register. This 8-bit register provides the system microprocessor with status information about the data transfer. Bit Function 7 Reserved, always 0. 6 Transmitter shift register empty (TEMT). This bit is set to 1 when the transmitter holding register and the transmitter shift register are both empty. This means that all data has been sent out of the controller. 5 Transmitter holding register empty (THRE). This bit indicates that the serial controller is ready to accept a new character for transmission. This bit is set to 1 when a character is transferred from transmitter holding register into the transmitter shift register. This bit is cleared to 0 when the system microprocessor loads the transmitter holding register. This bit also causes the controller to issue an interrupt to the system microprocessor when the bit 1 in the interrupt enable register is set to 1. 4 Break interrupt. This bit is set to 1 when the received data input is held in the spacing state for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). Bits 1 through 4 are the error conditions that produce a receiver line status interrupt whenever any of the corresponding conditions are detected. 3 Framing error (FE). This bit is set to 1 when the stop bit, following the last data bit or parity bit is at a spacing level. This indicates that the received character did not have a valid stop bit. 2 Parity error (PE). This bit is set to 1 when a parity error is detected and cleared to 0 when the system microprocessor reads the line status register. 1 Overrun error (OR). When set to 1, this bit indicates that data in the receiver register was not read by the system microprocessor before the next character was transferred into the receiver buffer register, destroying the previous character. This bit is also cleared when the system microprocessor reads the line status register. 0 Data ready (DR). This bit is set to 1 when a complete incoming character has been received and transferred into the receiver buffer register. This bit is cleared to 0 by reading the receiver buffer register. Modem status register (hex nFE) This 8-bit register provides the current state of the control lines from the modem (or external device) to the system microprocessor. In addition, bits 3 through 0 of this register provide change information. These four bits are set to logical 1 whenever a control input from the modem changes state. They are reset to 0 whenever the system microprocessor reads this register. Bit Function 7 Data Carrier Detect (DCD). This bit is the inverted data carrier detect modem control input signal. In diagnostics mode, this bit is connected to bit 3 in the modem control register. 6 Ring Indicator (RI). This bit is the inverted ring indicator modem control input signal. In diagnostics mode, this bit is connected to bit 2 of the modem control register. 5 Data Set Ready (DSR). This bit is the inverted data set ready modem control input signal. In diagnostics mode, this bit is connected to bit 0 of the modem control register. 4 Clear to Send (CTS). This bit is the inverted clear to send modem control input signal. In diagnostics mode, this bit is connected to bit 1 of the modem control register. 3 Delta DCD. When set to 1, this bit indicates that the DCD modem control input signal has changed state since the last time it was read by the system microprocessor. Whenever bit 0, 1, 2, or 3 is set, a modem status interrupt is generated. 2 Trailing Edge Ring Indicator. When set to 1, this indicates that ring indicator modem control input signal has changed from and active condition to an inactive condition. 1 Delta DSR. When set to 1, this bit indicates that the DSR modem control input signal has changed state since the last time it was read by the system microprocessor. 0 Delta CTS. When set to 1, this bit indicates that the CTS modem control input signal has changed state since the last time it was read by the system microprocessor. Scratch Register This register does not control the serial port in any way. It can be used by the system microprocessor to temporarily hold data. --- This text is from PS/2 reference manual. I left out some unimportant parts and added some comments which I wish someone had told me when I began the communications programming. Have fun, and sorry for any typos. Madis Kaal, aka Mast of 2:490/30@fidonet.org